This Display 101 article will discuss the digital parallel RGB interface and how the row and column driving signals are generated from the digital parallel RGB interface.
TFT panel working principle
Firstly, let’s introduce you to the basic working principle of a TFT panel.
An LCD display is composed of an array of liquid crystal segments. The crystal itself doesn’t emit light. When there is no electrical field, crystals are organized in a random pattern. When an electric field is applied, the crystals align to the electrical field. Various strength of electric fields works like a “gate” to pass different intensity of backlight through the crystals. When the crystals are aligned perpendicular to the backlight, backlight can’t pass through the crystals. 
From the view of electronic structure, an LCD panel consists of a grid of electrical signals. The pixels are addressed by a matrix where every interaction belongs to a pixel. Each pixel is connected perpendicularly to row and column through a transistor. When the row and column are selected by an IC controller, the responding pixel at the interaction of the row and the column is enabled or disabled. 
Figure 1.1 The electronic structure of an LCD panel 
Generating a specific color for a pixel
To generate a specific color for a pixel, 1 pixel is composed of 3 segments which individually pass light through a red, green and blue filter to make an RGB pixel. For a 320*240 RGB TFT display, there are actually 960 (320*3) columns and 240 rows.
Figure 1.2 The matrix arrangement of pixels of an LCD panel 
Most LCD displays have a digital parallel RGB interface, which is between the graphic controller as a signal source and the input of the display module.
The RGB interface is responsible for sending the image data information (grey level and color) in real-time.
The image data is transmitted digitally as “0 ”or “1 “ by TTL voltage levels. For the RGB interface, each of the signals has a corresponding line. Below are the signal connections of the RGB interface of 24 bits per pixel.
Figure 1.3 A example of TFT signal connections (24bpp) via parallel RGB interface 
What is a parallel RGB interface made out of?
So, the digital parallel RGB interface is composed of the following basic timing signals: 
- VSYNC (vertical Sync for TFT), used to reset a new frame.
- HSYNC (Horizontal sync for TFT), used to reset the LCD next line or row
D0….dXX (every bit has a separate line )
- LCDCLK (LCD clock) used to synchronize gray level data.
Figure 1.4. The frame and line timing parameters of a parallel RGB interface 
The vertical synchronization VSYNC sets the start of a new frame. There are no image data during the VSYNC sync pulse which are marked with VBP and VFP. 
The same principle is applied for the HSYNC sync pulse, marked with HBP and HFP. The HSYNC pulse is responsible for a new row. Between two HSync pulses, the grey level RGB color data for one row (line) have to be transmitted. 
As the TFT display can drive 3 segments (1 pixel) per clock, the length of LCDCLK is determined by the number of columns of the resolution.
For example, the resolution of a TFT display is 480*272, we assume the below parameters: 
So based on Figure 3. we can obtain:
- A single line takes (2 + 2 + 41 + 480) clocks = 525 clocks/line
- A full-frame takes (2 + 2 + 10 + 272) lines = 286 lines/frame
- A full-frame in clocks = 286 * 525 = 150150 clocks/frame
For clock speed with 7.83MHz, the LCD would refresh at 7.83M/150.15K = 52.1Hz
: How TFT works. https://www.tomshardware.com/reviews/tft-guide,114-4.html
[2 ]: Philips. ”Introduction to graphics and LCD technologies”
: Chen, Janglin, Wayne Cranton, and Mark Fihn, eds. Handbook of visual display technology. Berlin/Heidelberg, Germany: Springer, 2016.
: Watkinson J, Rumsey F (2003) Chapter 3: Digital transmission, Chapter 7: Digital video interfaces. In: Digital interface handbook. Focal, Burlingto